In the process of integrated circuit development, the design of the electronic circuit to be developed is generally laid out by a logic designer. The logic designer defines the specific implementation of a desired function, partitions this function into logically coherent chunks, so-called macros, and defines primary input and output pins of these macros. In this context, the term “macro” is used to denote a design of a logic function on a chip and specifies the interconnection of the required logic elements as well as the physical pathways and wiring patterns between the components of the macro. In order to reflect the hierarchical structure of a design unit in terms of macros, the design is typically described in terms of a hierarchical netlist or in terms of a hardware description language such as hierarchical VHDL. Specifically, the macros proper may be described in macro VHDL, whereas the connectivity of the macros within the unit may be described in unit VHDL.
Once the logic designer has desired function in terms of a hierarchical description, for example in a hardware description language such as VHDL or Verilog, an automatic tool such as a Random Logic Macro generator RLM may generate (synthesize) a physical electronic layout corresponding to the logic structure of electronic design unit. If automatic synthesis does not yield a satisfactory result, it may be supplemented or replaced by manual placement and routing by a custom designer.
Subsequently, the macros thus synthesized are placed on the chip and have to be wired in such a way as to meet predetermined requirements related to timing, signal accuracy etc. This process step of placing and wiring the macros is carried out by a unit integrator, based on a so-called “macro abstracts” which relate to the physical properties of the macros such as size, shape, pin position etc. The unit integrator thus places the macros onto the unit and routes all connections between the macro pins and to/from the unit pins. The unit integrator typically handles macros and macro abstracts as black boxes. In this context, the unit itself can be considered as a large macro, comprising macro abstracts, macro pins and unit pins.
In order to avoid conflicts during integrated circuit design, the usage of resources (e.g. amount of wiring space and wiring levels) within the unit is negotiated between the logic designer and the unit integrator in terms of contracts regulating the amount and specifics of resources to be used by logic design and unit integration. As an example, the synthesis program (or the custom designer) which translates macro VHDL code of a given macro into a physical implementation of that macro, is assigned predefined wiring resources specified by this macro's contract; these resources are then blocked for all other macros. Given that a unit may contain hundreds of macros, negotiating the corresponding contracts while taking into account routing restrictions is a formidable task.
As the design is wired, buffered and verified, macro size and shape, pin position etc. as well as available resources such as wiring levels, blockages etc. are contracted iteratively between unit integrator and logic designer. This negotiation process uses up a lot of time and resources: Whenever the logic designer makes a modification (such as changing the pin number and/or pin position) to a macro, this requires the unit integrator to readjust macro abstracts and wiring on the chip. This is an iterative process in which macro abstracts are passed back and forth and negotiated between the logic designer and the unit integrator. The logic designer may make modifications (such as changing the number of pins and/or pin position) within a specific macro which may in turn require the unit integrator to readjust one or several macro abstracts on the chip. These modification steps are cumbersome and error-prone and lie beyond the key tasks of the unit integrator. Moreover, this process brings about blockages (regions of the chip which are unavailable for placing a given macro) which are based on assumptions and may be wrong or waste resources.
Thus, there is a need of an electronic design automation (EDA) tool which relieves the unit integrator from the task of manually adjusting macro abstracts when a modification in a macro cell has occurred.